The invention relates to telecommunications and more particularly to a fault tolerant switching architecture.
Switching systems are taking an essential place in telecommunication networks. The first switches were based on cross-connect techniques providing the capability of switching at high rates.
The introduction of Asynchronous Transfer Mode (ATM) for multimedia applications mixing voice, data and video, as well as the development of electronic business and transaction equipment revealed the interest in switching architectures capable of handling small packets of data. In this respect, shared buffer techniques permit associating a high switching rate while handling the small packets of data. Basically, in this shared buffer switching technique, a central buffer is used for storing the messages which are received from the input ports of the switch before they are re-routed towards the appropriate output ports. Each output port of the switch is associated with an output queue which stores the succession of addresses corresponding to the location of the different messages loaded in the buffer, prior to their extraction and delivery to the considered output port. The queuing process is located at the output level of the switch, which eliminates the xe2x80x9chead of line blockingxe2x80x9d drawback and also facilitates multi casting capabilities. Shared buffer switches can be enhanced by means of speed expansion and port expansion mechanisms. Examples of such shared buffer techniques can be found in the non-published European Patent Applications No. 97480057.5, 97480056.7, 97480065.8, 96480129.4, 96480120.3 assigned to the assignee of the present application (IBM Docket FR996040; IBM Docket FR996042; IBM Docket FR996043; IBM Docket FR996044; IBM Docket FR996045) which are herein incorporated by simple reference. Additional prior art documents relating to shared buffer switching techniques can be found in non-published European Patent Applications No. 97480100.3 (IBM Docket FR997047), No. 97480098.9 (IBM Docket FR997048), No. 97480101.1 (IBM Docket FR997049), No. 97480099.7 (IBM Docket FR997050), No. 98480007.8 (IBM Docket FR 997053) and No. 98480006.0 (IBM Docket FR997055).
Whatever the particular technique being used, the traditional cross-connect or the newly developed shared buffer technique, switching systems should incorporate some kind of fault tolerant mechanisms which provide them with the capability of ensuring a continuous switching process even in case of an abnormal condition. Telecommunication suppliers have provided recommendations for introducing mechanisms in telecom systems for minimizing the effects on the data of the occurrence of abnormal situations. A Bellmore recommendation specifies that, in case of a breakdown in one element of a switching equipment, the error data conveyed through that equipment should not exceed 50 milliseconds, while the data which are not conveyed through the equipment should not be impacted. Considering the example of a component attached to a particular port of a switch that falls in a breakdown condition, it is recommended that the data cells entering into the switch via the other ports should not be affected by the breakdown, while the particular data which should enter that port should be re-routed in less than 50 milliseconds.
The main object of the present invention is therefore to design a switching architecture, based on cross-connect or shared buffer technique, having fault tolerant mechanisms providing high availability of the switching resources.
It is also an object of the present invention to provide a switching architecture having the capability for automatic detection of error conditions occurring in one element of the architecture, and further including mechanisms for re-establishing the switching resources.
It is another object of the present invention to provide a breakdown detection and traffic reestablishment mechanism that is particularly well suited for the shared buffer switches and permits port expansion and buffer expansion capability.
These and other objects of the present invention are attained with the fault tolerant switching architecture which includes a first and a second switch fabric including a first and a second switch core, respectively, located in a centralized building and a set of Switch Core Access Layer (SCAL) elements distributed in different physical areas. Each SCAL element contains a SCAL receive element and a SCAL transmit element for respectively permitting access to a corresponding input and output port of the switch core. A set of port adapters is distributed at different physical areas, and each is connected to the first and second switch fabrics via a particular SCAL element so that each switch core receives the sequence of cells coming from any port adapter and conversely any port adapter may receive data from either one of the first or second switch cores. Each switch fabric includes means for detecting an internal breakdown condition occurring in one of its components and means for transferring an error control signal to the peer element located in the other switch fabric.
Preferably, in each switch core there is provided means for extracting the Switch Routing Header (SRH) from the cell entering into the switch core, and means for addressing a routing table with the contents of the SRH for getting a bit map value representing the output ports to which the cell should be routed. An additional controllable masking mechanism is used for altering the value of the bit map in response to the detection of the error control signal from the peer switch core. The routing process is then performed with the altered value of the bit map.
In a preferred embodiment, the masking mechanism is also controlled by the value of a Filtering Control field which is extracted from the SRH contained in every entering cell, and each SCAL receive element includes means for altering the value of the Filtering Control field in response to the detection of an error control signal received from the peer SCAL receive element.
In a preferred embodiment of the invention, an 8B/10B coding scheme is used for the introduction of additional error detection capability.